1. Field of the Invention
The present invention relates to a data processing apparatus and method for computing an absolute difference between first and second data elements, and in particular between a portion of the first and second data elements.
2. Description of the Prior Art
For two data elements, the absolute difference is the magnitude of the difference between the two data elements, expressed as a positive value. When performing a data processing operation on first and second data elements, there are many instances where as part of that data processing operation it is necessary to compute the absolute difference between a portion of the two data elements.
One known approach for performing such an absolute difference computation is to use an end around carry adder, followed by a ones complement operation if negation is required. If the two data element portions are A and B, data element portion B is inverted and added to data element portion A within the end around carry adder. If A is larger than B, then this will be indicated by a logic zero value in the most significant bit position of the output from the end around carry adder, and in such instances no negation is required. However, if A is less than B, then the output from the end around carry adder will be negative (as indicated by a logic one value in the most significant bit position), and the negation of the result is required in order to produce the absolute difference value.
One problem with using the end around carry adder approach is that an end around carry adder is relatively slow when compared with a normal adder. This speed problem is compounded by the fact that the selection of the adder's output or the inverted version of the output can only be made once the most significant bit of the output from the end around carry adder is known, which adds further time delay in the generation of the absolute difference value.
As there is a general desire to perform data processing operations more and more quickly, this tends to lead to reduction in the clock period (also referred to herein as cycle time) within the data processing apparatus. As the cycle time reduces, the time taken by an end around carry adder to compute an absolute difference value can become unacceptable.
An alternative approach for computing an absolute difference value is to determine which of the two data elements is the largest, and then to swap the ordering of the data element portions if required so that a normal adder can be used to compute the absolute difference value. The detection of which data element is the largest can often be performed in a clock cycle prior to the clock cycle in which the computation of the difference takes place within the adder. Nevertheless, as cycle times decrease, there may be insufficient time to perform any required swap, followed by the addition, within a single clock cycle.
Accordingly, it would be desirable to provide an improved technique for computing an absolute difference between portions of first and second data elements.